1. Field of the Invention
The present invention relates to improvement of a semiconductor device having a ball grid array.
2. Description of the Related Art
FIG. 1 shows a conventional semiconductor device having a ball grid array.
Ball bumps 2 are formed on a main surface of an LSI (large scale integrated circuit) chip 1. The bumps 2 are formed of metal such as solder.
A chip carrier 3 comprises a laminate board 4 having a plurality of layers, wires 5 passing through each layer and each interlayer, electrodes 6a formed on one surface side of the laminate board 4, and electrodes 6b formed on the other surface side of the laminate board 4.
The wires 5 electrically connect the electrodes 6a to the electrodes 6b. The electrodes 6b are arrayed on the other surface side of the laminate board 4. Ball electrodes 7 are formed on the electrodes 6b, respectively. The ball electrodes 7 constitute a ball grid array. The ball electrodes 7 are formed of metal such as solder, etc.
The LSI chip 1 is combined with the electrodes 6a of one side of the laminate board 4 by the ball bumps 2. As a result, the LSI chip 1 is brought into contact with the ball electrodes 7.
The following will explain the features of the above-explained semiconductor device having the ball grid array.
The first feature lies in that the mount of the semiconductor device can be easily performed.
Specifically, as shown in FIG. 2, a semiconductor device 100 is placed on a print circuit board 200, and heat is applied thereon, so that the mount of the semiconductor device can be completed.
As shown in FIG. 3, the print circuit board 200 on which the semiconductor device 100 is mounted is moved via a reflow furnace 300. The ball electrodes 7 of the semiconductor device 100 are temporarily melted when entering the reflow furnace 300. Then, when the electrodes 7 come out of the reflow furnace 300, the ball electrodes 7 are solidified again. At the time when the ball electrodes 7 are solidified again, they are combined with electrodes 8 of the print circuit board 200.
The second feature lies in that the semiconductor device can be miniaturized.
As shown in FIG. 4, the LSI chip 1 is combined with the electrodes 6a of the chip carrier 3 by the ball bumps 2. As a result, the semiconductor device of FIG. 1 can be miniaturized by a width H as compared with a semiconductor device having a bonding wire 9 (Japanese Patent Application H3-22337).
Next, the following will explain the disadvantages of the above-explained semiconductor device having the ball grid array.
As shown in FIG. 3, in the reflow furnace 300, heat is applied to the ball bumps 2 as well as the ball electrodes 7. In this case, if the ball electrodes 7 and the ball bumps 2 are formed of the same material, the melting point for electrodes 7 becomes the same as the melting point for the ball bumps 2. As a result, when the ball electrodes 7 are melted, the ball bumps 2 are also melted, so that the shape of each bump is largely distorted.
To prevent the bumps 2 from being distorted, it is needed that materials for both bumps 2 and the ball electrodes 7 be differed from each other. Thereby, the melting point of the material for the bumps 2 must be set to be higher than that of the material for the ball electrodes 7.
Conventionally, the ball electrodes 7 are formed of eutectic solder containing, for example, Sn (tin) of 63 wt %, and Pb (lead) of 37 wt %. The ball bumps 2 are formed of high melting point solder containing Sn of 3 wt % and Pb of 97 wt %.
FIG. 5 is a phase diagram showing a phase of an alloy containing Sn and Pb in a case where temperature and composition are set as parameters (constant pressure).
In FIG. 5, a point E is an eutectic point, a point A is a melting point of Pb, and a point D is a melting point of Sn. A line connecting points A, E, and D is a boundary line between a solid phase and a liquid phase.
As shown in FIG. 5, in the case of the alloy (solder) formed of Sn and PB, if a Sn content and a Pb content are 63 wt % and 37 wt %, respectively, the allow becomes eutectic, and its melting point is about 183.degree. C.
If the Sn content and the Pb content are 3 wt % and 97 wt %, respectively, the melting point is about 320.degree. C.
In other words, the bumps (high melting point solder) 2 are formed of the alloy having of Sn of 3 wt % and Pb of 97 wt %, and the ball electrodes 7 are formed of the alloy having of Sn of 63 wt % and Pb of 37 wt %. As a result, the melting point of each bump 2 is higher than that of each ball electrode 7.
However, in a case where the melting point of each bump 2 is higher than that of each ball electrode 7, the following disadvantage will occur.
Generally, the melting point of each bump 2 results in an extremely high value exceeding 300.degree. C. (for example, about 320.degree. C.).
Due to this, the laminate board 4 of the chip carrier 3 must be formed of material, which can resist against the extremely high heat exceeding 300.degree. C. not to cause deformation and distortion.
However, for the present, there is no other material than ceramics such as alumina ceramics, which can resist heat exceeding 300.degree. C. and which can fully function as chip carrier 3. However, since such ceramics are expensive, the manufacturing cost of the semiconductor device will be increased.